In memory cells for use with memory matrices of the type employing an electrically floating gate such as described in "Electronics" of Feb. 28, 1980, pp. 113 through 117, faulty insulating layers, for example, between the control gate and the storage gate and between the regions and the storage gate, may lead to unintended reprogrammings because of excessive leakage currents. Therefore, the memory cells must be subjected to a test following manufacture such as described in DE-OS No. 30 30 852 and the published documents of the application WO No. 82/00154. These publications pertain to testing methods for an electrically programmable memory matrix employing "n" row selecting lines via which "m" memory cells are capable of being selected, and which are connected to each time one of "n" outputs of a row decoder having "a" input terminal pairs according to the relationship n=2.sup.a. Into the row decoder, depending on the mode of operation, are fed a ground potential Vo which is approximately zero potential, a supply potential Vcc of about 5 V, and a programming potential Vp of e.g., 25 V. For conventional types of programmable memory matrices during normal operation (writing, erasing, reading), first input signals are each applied to one terminal of the "a" input terminal pairs of the row decoder and second input signals which are complementary to the first input signal are each applied to the other terminal of each pair.
For test operations, each of the "a" address amplifiers supplying the input terminal pairs includes an additional activating terminal to which an activating signal level is applied for test actuation. When the activating signal level is applied, all row selecting lines are capable of being switched to a high level necessary for the programming.
The application WO No. 81/00154 proposes to carry out a test operation by applying a test voltage simultaneously between the control gate and the source of each memory transistor during a certain period of time. According to the test method disclosed in DE-OS No. 30 30 852, it is proposed to passivate the address amplifiers by means of the additional circuit, so that all row selecting lines are simultaneously capable of being switched to the level necessary for the programming operation, to feed the programming voltage into the decoder and, finally, to test in the course of a reading process following the test, whether reprogramming has taken place in the memory cells due to a leakage current mechanism.
Accordingly, with the aid of the conventional additional circuits, it is possible to carry out a test operation in which all memory cells can be subjected to a programming operation or can be simultaneously subjected to a voltage loading with the effects thereof being measured during a subsequent reading operation. Individual testing of the memory cells with respect to leakage points is practically out of the question because of the unbearable long testing time which would be required.
The conventional additional circuit for testing a memory matrix has the disadvantage that cells lying next to each other cannot be tested with respect to a mutual influencing or interaction.